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High Performance Computing Laboratory

Texas A&M University College of Engineering

A Heuristic for Peak Power Constrained Design of Network on Chip (NoC) based Multimode System

P. S. Bhojwani, R. N. Mahapatra and E. J. Kim

Proceedings of Intl. Conf. on VLSI Design, IEEE Computer Press, 2005.

Designing NoC-based systems has become increasingly complex with support for multiple functionalities. Decisions regarding interconnections between the heterogeneous system components and routing of system communication affect system performance and power consumption. This research provides a heuristic to determine the neighborhood configuration for each component. By controlling the communication bandwidth allocation, simulation results with synthetic and real workloads indicate that our heuristic is able to control the peak power consumption, but at cost of throughput degradation.

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